Historically there have been various methods for data clock recovery whereby the data could be recovered in optimal fashion. These methods required a certain number of bits prior to the information in order to recover the data clock in question.
Frequently the specifications of present-day burst mode communication systems require a very short preamble in order to increase the frame efficiency, and in which the clock signal has to have been recovered in order to regenerate the data.
As a consequence of this, new methods have appeared with the objective of fast recovery of data clock synchronization. Many of these are based on sampling the input data with several samples per bit; these samples are then processed as described in the article "A Bit Synchronization Technique for PDS Optical Subscriber Loop Systems" by Masakazu Kitazawa et al., published in the Proceedings of the "Workshop on Local Optical Networks" by the IEEE, Tokyo, Japan, 1991.
This article, on page 8.2-4, shows a block diagram of a fast bit synchronization circuit in which four bit rate clocks are generated with uniformly distributed phases and which are used for the sampling of the incoming data so that, subsequently, a detector circuit can determine which of the differently phased clocks best adapt to the incoming data.
The operating principle is based, as shown in FIG. 6 of the article mentioned, on carrying out an exclusive-OR function with two consecutive samples to detect the transitions of the data. The results of the preceding operations are progressively stored in a register, decoding of which serves to select the clock with the best phase.
In this method, bit synchronism is achieved after several bit periods.